V-FPGAs: Increasing Performance with Manual Placement, Timing Extraction and Extended Timing Modeling

Abstract Virtual FPGAs (V-FPGAs) are used as vendor-independent virtualization layers, to retrofit features which not available on the host FPGA and prototype novel architectures. In these usecases, achievable clock frequencies of V-FPGA user applications a major concern. The abstraction layer inherently induces overhead, but this aspect is reinforced by nonuniformity effects: When cells perform worse locally, basic architecture modeling generalizes worst-case path delays whole device, limiting lower frequency than theoretically achievable. We propose three approaches attenuate First we introduce uniformity metrics manual placement strategies for more uniform placement, improving 16 %. Second, framework automated timing extraction, enabling individual characterization each design. Third, after evaluating Vivado synthesis strategies, extend model non-uniform timings, achieving improvements up 28